? isolation : meets or exceeds 802.3 ieee requirements ? characteristic filter impedance : 100 w ? (1) referenced @ 5 mhz response. insertion loss (db max.) common mode rejection (db min.) crosstalk (db min.) return loss (db min.) -1 -15 1-10 mhz @ 50 mhz -20 -10 @ 100 mhz -30 -30 -30 @ 1-10 mhz 5-10 mhz @ 25 mhz @ 30 mhz @ 40 mhz xmit rcv xmit rcv xmit rcv xmit rcv xmit rcv xmit rcv xmit rcv -25 -1 -15 -30 -25 electrical parameters @ 25 c 10 base-t interface module cse6199sa rev.- 6/5/97 ? optimized for level one lxt905 ? ? two pairs of tx and rx in 40 pin soic package ? ? robust design allows for toughest soldering process ? ? complies with or exceeds ieee 802.3, 10 base-t requirements ? schematic epe6199s group delay (ns max.) 3 e l e c t r o n i c s i n c . --- xmit rcv attenuation (db min.) (1) 5-10 mhz tel: (818) 892-0761 fax: (818) 894-5791 http://www.pca.com pca electronics, inc. 16799 schoenborn st. north hills, ca 91343 --- --- --- a b c d e f g h i (j) k l m n p q r s dim. 1.105 .470 .200 .950 .005 .050 .620 .016 .008 .083 0 .025 .200 .250 min. 1.125 .490 .220 typ. .015 typ. .640 .022. .012 typ. 8 .045 typ. typ. max. .030 .050 .090 .670 2 plcs 2 plcs nom. (inches) (millimeters) 28.67 11.94 5.08 24.13 .127 1.27 15.75 .406 .203 2.10 0 .635 5.08 6.35 min. 28.58 12.45 5.59 typ. .381 typ. 16.26 .559 .305 typ. 8 1.14 typ. typ. max. .762 1.27 2.29 17.02 2 plcs 2 plcs nom. dimensions package f solder pad layout pca epf6199s date code b q n m p 120 21 40 c l i g e d h a k (j) transmit channel receive channel 38,27 40,29 39,28 3,13 2,12 1,11 1:2 lpf 12.4 w 12.4 w 33,22 34,23 9,19 8,18 10,20 1:1 100 w r s product performance is limited to specified parameters. data is subject to change without prior notice.
cse6199sb rev. - 6/5/97 10 base-t interface module e l e c t r o n i c s i n c . epe6199s tel: (818) 892-0761 fax: (818) 894-5791 http://www.pca.com pca electronics, inc. 16799 schoenborn st. north hills, ca 91343 the circuit below is a guideline for interconnecting pcas epe6199s with lxt905 10 base-t phy chip over utp cable. further details of system design, such as chip pin-out, etc. can be obtained from the specific chip manufacturer. typical insertion loss of the isolation transformer is 0.7db. this parameter covers the entire spectrum of the encoded signals in 10 base-t protocols. however, the predistortion resistor network introduces some loss which has to be taken into account in determining how well your design meets the standard template requirements. additionally, the following need to be considered while selecting resistor values : a. each channel needs 100 w termination, thus the thevenins equivalent resistance seen by a channel looking into the transmit outputs from the chip must be equal to a value close to 100 w . the lxt 905 driver output impedances are very low. . thus only 11.8 w on tpon & tpop are enough to provide a balanced 25 w termination given that turns ratio is 1:2. following these guidelines will guarantee that the return loss specifications are satisfied at all extremes of cable impedance (i.e. 85 w to 115 w ) while the module is installed in your system. the receiver channel termination is rather straight forward: two 50 w loads provide the balanced termination to the cable. b. that the template requirements are satisfied under the worst case vcc (i.e. 4.5v), will impose a further constraint on resistor selection, in that they ought to be the minimum derived from the calculations. users can allow for pads on their pcb for a shunting resistor across pins 6 and 8 of epe6199s for more flexibility in setting voltage levels at the outputs. note that some systems have auto polarity detection and some do not. if not, be certain to follow the proper polarity. the pulldown resistors used around the rj45 connector have been known to suppress unwanted radiation that unused wires pick up from the immediate environment. their placement and use are to be considered carefully before a design is finalized. it is recommended that there be a neat separation of ground planes in the layout. it is generally accepted practice to limit t he plane off at least 0.08 inches away from the chip side pins of epe6199s. there need not be any ground plane beyond this point. for best results, pcb designer should design the outgoing traces preferably to be 50 w , balanced and well coupled to achieve minimum radiation from these traces. typical application circuit for utp for one port only. lxt905 phy rj45* 3 6 2 1 tpin tpip tpon tpop epe6199s tx+ tx- rx+ rx- 9 8 notes : * pin-outs shown are for hubs and repeaters. chassis ground 8 7 45 39 38 2 3 34 33 0.1 m f x7r high voltage cap, if use d 2kv recommende d 0.1 m f x7r 1 10
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